Chip-lifetime testing instrument for semiconductor devices

ABSTRACT

A chip-lifetime testing instrument for semiconductor devices which can detect defective chips by testing the performance and electrical lifetime of the chips in manufacturing process of the semiconductor devices, so that the manufacturing cost can be reduced and unnecessary processes for packaging of defective chips can be avoided, thereby reducing the necessary space for the set-up of the testing instrument.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor manufacturinginstrument, and more particularly to, a chip-lifetime testing instrumentfor a semiconductor device which can detect inferior chips by testingthe performance and electrical lifetime thereof in the manufacturingprocess of the semiconductor devices.

In general, the chip-lifetime test of semiconductor devices has beencarried out after packaging chips by loading, wire-bonding, and moldingprocesses and the test has been achieved by connecting the externallyexposed leads of a package to power supplying means of a chip-lifetimetesting instrument.

Since the performance and electrical lifetime test of the chip iscarried out in the packaged state, therefore, unsatisfactory chips havealready been packaged, reducing the efficiency of production andresulting in substantial cost such as the waste of materials due topackaging unsatisfactory chips.

Also, the testing instrument for the packaged chip must be large inorder to be connected electrically to the externally exposed leads ofthe package. Thus, the set-up cost increases and large spaces areneeded.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a chip-lifetime testinginstrument of semiconductor devices which carries out the performanceand electrical lifetime test of a fabricated semiconductor device in achip state before packaging so as to reduce the cost by removingunnecessary processes for packaging unsatisfactory chips and alsoreducing the necessary space for the set-up of the testing instrument.

According to the present invention, there is provided a chip-lifetimetesting instrument for semiconductor devices, comprising: a tray havinga slot for holding a chip, probes in contact with electrodes of thechip, a substrate having circuit patterns for electrical testing of thechip and connected to the end of each probe, and a clamp for fixing thesubstrate with respect to the tray.

Further characteristics and advantages of the present invention willbecome clear from the detailed description with reference to theappended drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1-3 are perspective and cross-sectional views of a preferredembodiment of a chip-lifetime testing instrument according to thepresent invention.

FIGS. 4-6 are cross-sectional views for illustrating the structure ofanother embodiment of a chip-lifetime testing instrument according tothe present invention.

FIG. 7 and 7A are plan views of the chip-lifetime testing instrument asshown in FIG. 2 or FIG. 5, and

FIGS. 8 and 8A are plan views of the chip-lifetime testing instrument asshown in FIG. 3 or FIG. 6.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 1 and FIG. 2 show a chip-lifetime testing instrument which cancarry out the chip-lifetime test of a chip 1 without forming bumps onelectrodes 1a.

The chip-lifetime testing instrument comprises a tray 2 having a slot 2ato hold the chip 1 safely, a substrate 4 having circuit patterns forlifetime testing, probes 5 of which one side is connected to eachcircuit pattern of the substrate 4 and the other side is connected toeach electrode of the chip 1 to electrically connect them to each other,and a clamp 6 for fixing the substrate 4 relative to the tray 2.

The side of each probe to be in contact with each electrode of the chip1 is bent and tips 5a are formed at each end portion to play a bufferingrole against the electrode 1a of the chip 1.

In order to accurately align the tips 5a of the probes 5 with theelectrodes 1a of the chip 1, the upper sides of the probes 5 are exposedthrough an opening in the substrate 4 or a viewing window 7 made of atransparent material can be formed as shown in FIG. 3.

In case the upper sides of the probe 5 are open as shown in FIG. 2,various types of markings 8a and 8b are formed on predeterminedpositions of chip 1 and the corresponding positions of the substrate 4as shown in FIG. 7.

Similarly, in the case of the window 7 at the upper sides of the probe 5as shown in FIG. 3, various of markings 8c and 8d are formed onpredetermined positions of chip 1 and the corresponding positions of thewindow 7, respectively, as shown in FIG. 8.

On the other hand, FIG. 4 and FIG. 5 show another chip-lifetime testinginstrument in a chip 11 for which bumps 19 are formed on electrodes 11a.

This chip-lifetime testing instrument comprises a tray 12 having a slot12a to hold a chip 11 safely, a substrate 14 having circuit patterns forlifetime testing, probes 15 of which one side is connected to eachcircuit pattern of the substrate 14 and the other side is connected toeach bump formed on the electrode 11a of the chip 11 to electricallyconnect them to each other, and a clamp 16 for fixing the substrate 14.

The end portion of each probe to be in contact with the bump 19 of thechip 11 is flat and at the bottom of the end portion of each probe 5tips 15a are formed to act a buffering role while contacting the bump 19of the chip 11.

Also, a viewing window 17 can be formed on the upper side of the probes15 as shown in FIG. 6 similarly to the instrument in which the bumps arenot formed.

If the upper sides are open of the probe 15 as shown in FIG. 5, variousmarkings 18a and 18b are formed at predetermined positions of the chip11 and at corresponding positions of the substrate 14 as shown in FIG.7, while in case of forming the perspective window 17 as shown in FIG.6, markings 18c and 18d are formed at predetermined positions of thechip 11 and their corresponding positions of the window.

In the present invention described above, the chip 1 which has no bumpon the electrode 1a is inserted into the slot 2a of the tray 2 as shownin FIG. 1 or FIG. 2 and, next, the tips 5a of the probes 5, which areconnected to the circuit patterns 3 of the substrate, are in contactwith the electrodes 1a of the chip 1 by engaging the clamp 6 in a step26 formed in the tray 2 around the slot 2a, as shown in FIG. 2, so thatthe substrate 4 is fixed relative to the tray 2.

Here, the tips 5a act a buffering role so that the circuit patterns 3are certainly connected to the chip 1 without damage on the electrodes1a.

Since the markings 8a and 8b are formed at the predetermined positionsof the chip 1 and their corresponding positions of the substrate 4, thetips 5a of the probes 5 and the electrodes 1a of the chip 1 can beeasily aligned with each other by aligning the markings 8a and 8b.

Thus, the performance and lifetime test of the chip 1 are carried outsimply since the electrodes 1a of the chip 1 are electrically connectedto the circuit patterns 3 through the probes 5.

Also, if the perspective window 7 of the transparent material is formedat the upper side of the probe 5 as shown in FIG. 3, the chip 1 can beprotected from contamination materials such as external dust during theconnection state of the electrodes 1a with the tips 5a.

In addition, if the marking 8d is formed at the perspective window 7corresponding to the marking 8c of the chip 1, the alignment for acontact with the electrodes 1a of the chip 1 and the tips 5a of theprobes 5 becomes easier.

As another embodiment, in the case of forming the bumps 19 on eachelectrode of the chip 11 as shown in FIG. 4 and FIG. 5, the chip 11having the bumps 19 is inserted into the slot 12a of the tray 12 and,next, the tip 15a of the probe 15 is electrically connected to thecircuit patterns 13 of the substrate 14, so that the substrate 14 isfixed by the clamp 16.

At this time, the probe 15 is flat since the bump 19 is formed on thechip 11.

The tip 5a of the probe 15 is substantially in contact with theelectrode 11a of the chip 11 through the bump 19 which acts thebuffering role to prevent damage on the electrode 11a.

Similarly to the chip-lifetime testing instrument of the chip 1 withoutthe bump, the markings 18a and 18b are formed at the predeterminedpositions of the chip 11 and the corresponding positions of thesubstrate 14, respectively, so that the alignment between the tip 15a ofthe probe 15 and the bump 19 of the chip 11 becomes easier.

Also, if the perspective window 17 is formed at the upper side of theprobe 15 as shown in FIG. 6, the same effect can be obtained by formingthe marking 18d at the perspective window 17 instead of the substrate14, corresponding to the marking 18c of the chip 11.

As mentioned above, the present invention can not only prevent the lossof materials and the unnecessary process but also minimize the size ofthe instrument by testing the lifetime in the chip state beforepackaging bad chips.

What is claimed is:
 1. An instrument for testing chips of semiconductordevices, comprising:a tray having a slot to hold a chip to be tested,said chip having an arrangement of electrodes thereon; a plurality ofprobes for contacting the electrodes on said chip; a substrate to whichsaid probes are connected, said substrate having circuit patternsconnected to said probes for electrical testing of said chip; saidsubstrate being substantially flat and said probes projecting from saidsubstrate substantially in the plane of said substrate, said probeshaving ends for contacting the electrodes; said substrate beingselectively mountable on said tray for bringing said ends of the probesinto contact with said electrodes; marking means on the chip and thesubstrate for indicating angular corresponding of the substrate and thechip and consequent correspondence of the probes and the electrodes; andmeans on said substrate for engaging said tray to align and fix the endsof said probes and said electrodes when the substrate is mounted on saidtray.
 2. The instrument according to claim 1, wherein said ends of theprobes include downwardly bent portion with tips for contacting saidelectrodes.
 3. The instrument according to claim 1, wherein said chipsand said substrate have respective corners at both of which said markingmeans are placed.
 4. The instrument according to claim 1, wherein saidsubstrate includes a viewing window covering said probes.
 5. Theinstrument according to claim 4, wherein said marking means are on bothsaid chip and said window.
 6. The instrument according to claim 1,wherein said slot is recessed in said tray.
 7. The instrument accordingto claim 6, wherein said means on said substrate for engaging said trayincludes a step around said slot and a clamp secured to said substrateand engaging in said slot upon mounting the substrate on the tray.